The present embodiments relate generally to switch-mode DC-DC converters, and more particularly, to nearly fully-digital synthesizable digital controllers for buck, boost, buck-boost and cuk switch-mode DC-DC converters, a method for switch mode control DC-DC conversion, and corresponding DC-DC converters.
Switch-mode DC-DC converters can step down, step up or invert, step down, and step up an input supply voltage, for generating one or more supply voltages as may be required in various electronic systems. A basic structure for a buck (step down), boost (step up), buck-boost (step up/down and invert) and cuk (step up/down and invert) converter is shown in FIGS. 1, 2, 3 and 4, respectively. The basic structure 10a,10b,10c,10d comprises a controller 12 (Control Circuit), passive components 14,18,22,16,20,24 (L,L1,L2,C,C1,C2), and two switching elements 26,28. The switching elements may comprise, for example, a power transistor 26 (SW) and a diode 28 (D), or two power transistors (not shown). Each DC-DC converter also utilizes an input supply voltage 30 (Vout) and a reference voltage 32 (Vref). The controller of the DC-DC converter compares the reference voltage 30 (Vref) with the DC-DC converter output voltage 34 (Vout), processes the difference signal with a compensator (not shown), and generates pulse width modulation (PWM) control signals that are provided to the power transistor switching elements (SW) to keep the DC-DC converter output voltage 34 (Vout) at the desired value, in spite of potential load changes at the load 36 (Load). Furthermore, the switching frequency of the power transistor switching elements 26 (SW) is determined by the rate of the control circuit clock 38 (CLK). Monitoring a difference between the reference voltage 32 (Vref) and the feedback signal 40 (Vfbk), the controller can maintain a desired output voltage 34 (Vout) by controlling a duty cycle of the signal driving the power transistor switching element 26 (SW). However, in traditional DC-DC converters, the controllers are implemented with Integrated Circuits (ICs) requiring complex analog circuitry, for which their design, implementation and fabrication are difficult, time-consuming, and costly.
Integration of analog circuitry presents several issues that are not present when integrating digital circuits. Analog circuitry typically requires longer design cycles. Analog circuitry also suffers from a lack of accurate models which can be used to detect failure and reduced performance problems, thus often necessitating costly chip re-spins. In addition, the physical layout of analog circuitry can strongly influence a corresponding performance of the analog circuit, both positively and negatively. Also, manufacturing process changes can adversely influence and/or necessitate redesign of an analog circuit. Still further, analog circuit performance is susceptible to temperature changes and aging, as well as, being susceptible to analog component precision. Furthermore, analog circuits are not suitable for applications which require very low supply voltages. Yet still further, radiation hardening of analog circuits, when required for particular applications, is difficult, lengthy and expensive. Moreover, testability of analog circuits is complicated, i.e., compared to a testability of digital circuits.
A common analog controller 12 for switch-mode DC-DC converters consists of an analog operational amplifier 42 with an analog compensation circuit 44 followed by an analog PWM circuit 46. The operational amplifier 42 computes a difference between a reference signal 32 and a feedback signal 40 and also implements the compensation circuit 44. The functional structure of a classic buck converter 10 with analog controller is shown in FIG. 5. The buck converter 10 of FIG. 5 uses a classic proportional-integral-derivative (PID) compensator which consists of an integrator and differentiator with proportional gain (i.e., OpAmp, R1, C1, and C2). The PID compensator circuit compensates for the phase shift introduced by an LC circuit of the DC-DC converter 10, thus providing loop stability. The tracking loop characteristic can be modified by changing the parameters of the PID compensator (OpAmp,R1,C1,C2). The PWM circuit 46 samples the output of the amplifier 42 at the rate of the clock (CLK) and converts it into pulses whose duration is proportional to the amplitude of the input samples. In the converter 10 of FIG. 5, the analog PWM circuit 46 is implemented with a saw-tooth oscillator 48 and a comparator 50; however, a triangle-wave oscillator could have been used instead. The comparator 50 of the PWM circuit 46 compares the saw-tooth signal with the input and produces a square-wave signal with the same frequency as the saw-tooth signal, but with a duty cycle depending on the result of the comparison, for example, as shown in FIG. 6. In this example, when the PWM input signal is higher than the saw-tooth signal, the comparator 50 output goes high, otherwise it goes low. However, the polarity of control signals depends on switch characteristics and for some switches it may be necessary to invert the comparator output. The performance of the switch-mode DC-DC converter 10 of FIG. 5 depends noticeably on the analog controller 10 characteristics. For instance, component precision, as well as changes due to temperature variations and aging, of the analog compensator circuit 44 can negatively affect the tracking characteristics of the corresponding switch-mode DC-DC converter 10.
While some controllers use digital compensators, the controllers still employ analog blocks such as analog-to-digital converters (ADCs) to digitize the difference signal and PWM circuits using delay lines to generate control signal pulses for the switch-mode DC-DC converter. As will be described further herein, a digital implementation of such PWM circuits would require an impractically high clock frequency. With reference now to FIG. 7, a buck converter 50 uses a controller 52 that includes a differential ADC 54, a digital PID compensator 56 followed by a low-pass filter 58 (LPF), and a digital pulse width modulation 60 (DPWM) circuit. In the buck converter 50 of FIG. 7, the difference between the reference voltage 32 and the feedback voltage 40 is digitized by the differential ADC 54, processed by a digital PID compensator 56, low-pass filtered 58, and converted into pulses by the DPWM circuit 60. Typically, the differential ADC 54 has eight (8) bits of resolution and could be implemented via two ADCs. As will be described later herein, the transfer function of a PID circuit 56 has a single pole at DC and two zeros. The criterion for placement of the zeros is mainly to reduce the phase shift introduced by the LC filter to achieve stability when the loop is closed and at the same time to optimize the tracking performance of the loop. Generally the zeros are not used to reduce the PID gain which tends to be very large at high frequencies. Rather, the reduction of large PID gain at high frequencies is performed by a low-pass filter 58 (LPF) placed after the PID compensator 56. To further reduce the gain, in some architectures the ADC 54 and PID compensator 56 are sampled at rates much higher than the switching frequency. In such a case, the low-pass filter 58 (LPF) would also decimate the signal produced by the PID compensator 56 to the switching frequency. When the reference 32 (Vref) is digital, as shown in FIG. 8, a single ADC 62 is used to digitize the feedback signal 40.
In an attempt to reduce the analog complexity, some controllers have used sigma-delta ADCs instead of the traditional analog ADCs in the structures of FIGS. 7 and 8. However, this does not solve the problem addressed by the present embodiments, because sophisticated analog circuits are still needed to implement these sigma-delta ADCs.
One example of a typical implementation of a digital PWM (DPWM) circuit 65 is shown in FIG. 9. The DPWM circuit 65 is a digital equivalent of the PWM circuit 46 described earlier for the analog controller 12 of FIG. 5. Digital signals of the DPWM circuit 65 have a similar behavior to analog signals of the PWM circuit as depicted in FIG. 6. Besides the switching clock CLK 38 used to sample the ADC 54,62 and compensator 56, the DPWM circuit 65 also requires a faster clock CLK_DPWM 62 whose frequency is two to the power of N times the frequency of CLK (i.e., 2N×frequencyCLK), where N is the number of bits of the input signal. The faster clock CLK_DPWM 62 is derived from the clock CLK 38 via a phase-lock loop 64 (PLL). The faster clock 62 is used to divide the switching period into two to the power of N increments (i.e., 2N increments). The counter 66 (Mod-N Counter) produces a saw-tooth signal with a number of steps equivalent to two to the power of N (i.e., 2N steps). An edge detector 68 (Rising Edge Detector) clears the counter 66 via the counter Clear input, which also sets the flip-flop 70 analog output (Q) to 1, whenever a new input sample (Digital Input) 72 is available. The flip-flop 70 output (Q) is set to 0, when the current output of the counter 66 is greater than the input value 72 (Digital Input). The digital input 72 is coupled to the non-inverting input of a comparator 74, and the output of the counter 66 is coupled to the inverting input of the comparator 74. The output of the comparator 74 is coupled to the input D of flip-flop 70. If the digital input value is 0 (i.e., Digital Input=0), then the pulse at the Analog Output (Q) of the flip-flop 70 lasts one cycle of CLK_DPWM 62; whereas, if the digital input value 72 is 1 (i.e., Digital Input=1), the pulse at the Analog Output (Q) of the flip-flop 70 lasts two cycles; if the digital input value 72 is 2 (i.e., Digital Input=2), then the pulse at the Analog Output (Q) of the flip-flop 70 lasts three cycles; and so on, up to the maximum input value 72 (i.e., Digital Input=(2 to the power of N) minus 1 (or 2N−1)) which produces a pulse lasting 2 to the power of N cycles of CLK_DPWM (or 2N cycles of CLK_DPWM), equivalent to a full cycle of CLK 38. Even though the DPWM circuit 65 of FIG. 9 is totally digital, its main drawback is that it requires a very fast clock, thus increasing design difficulties and power consumption. For instance, for a relatively small input resolution of 8 bits and a switching clock frequency of 2 MHz, the DPWM circuit 65 of FIG. 9 would already require a frequency of 512 MHz for CLK_DPWM 62. Considering that higher resolutions are usually required to reduce noise and limit cycles, the DPWM architecture of FIG. 9 is impractical in many cases.
Another way to create pulse width modulated pulses from an N-bit input value, without the need for a faster clock than the switching clock, is to use a tapped-delay line. A typical circuit for a tapped delay line 76 is shown in FIG. 10. The tapped-delay line 76 consists of two to the power of N delay elements 78 (i.e., 2N delay elements) connected to the inputs of a multiplexer 80 (e.g., 2N to 1 multiplexer). The total delay of the tapped delay line 76 is one cycle of the switching clock CLK 38. The delay elements 78 can be implemented with digital gates. When a new digital input 82 sample is available, the multiplexer 80 selects the tap (841,2,3, . . . , n, where n=2N) corresponding to the value of the new digital input sample (e.g. tap 841 is selected for Digital Input=0, tap 842 is selected for Digital Input=1 . . . tap 84n is selected for Digital Input=n−1). In addition, a short pulse generated from a pulse generator 86, in response to the clock 38, sets the latch 88 (Latch) to 1 and also propagates through the tapped-delay line 76. When the clock pulse reaches the selected tap (841,2,3, . . . n) based upon the digital input 82, the latch 88 is reset to 0, via the latch reset input 90 (Reset). In this way for each digital input 82, an analog output pulse is generated with a duration equivalent to its value. The tapped delay line 76 further includes a delay matching network 92 coupled between the output of the pulse generator 86 and a set (Set) input 94 of latch 88. Compared to the circuit of FIG. 9, the circuit of FIG. 10 has the advantage of requiring only the clock 38 CLK, but it has the major drawback of requiring delay elements 78 which must be custom designed to introduce the specified delay. The precision requirement grows with the number of bits of the input signal 82. In addition, calibration techniques might be required to prevent temperature and supply voltage changes or process variations from affecting the delay.
Other architectures for DPWM circuits combine sigma-delta modulators with DPWM circuits, as will be described with reference to FIG. 11, to reduce the clock requirements of the DPWM of FIG. 9. As shown in FIG. 11, the circuit architecture 96 includes a traditional sigma-delta modulator 98 with a multi-bit quantizer 100 (Q) followed by a DPWM circuit. At a parity of clock (CLK) 38, sigma-delta modulators achieve higher resolutions than PWM circuits. With typical switching clocks, a sigma-delta modulator can achieve higher resolutions than 9 bits with 2 or 3-bit quantizers. Since the number of bits of the DPWM input is now very small, the clock CLK_DPWM is no longer too high and the DPWM circuit 60 of FIG. 11 can be implemented with the architecture 65 of FIG. 9. In addition, the clock CLK_DPWM needs to be only 4 or 8 times faster than the clock CLK 38. However, to further reduce power consumption, some architectures use the DPWM structure of FIG. 10 based on a tapped-delay line in the DPWM circuit of FIG. 11, even though the design complexity increases due to the delay elements of the tapped-delay line.
Still other DPWM circuits add extra circuitry to generate two control signals to drive the two switching elements of a synchronized rectifier. In the later instance, such a circuit typically requires a higher clock than the switching clock to generate non-overlapping control signals.
In addition, attempts to reduce the analog complexity of a controller 52 for switch-mode DC-DC converters 50, such as shown in FIG. 7, by replacing the ADC 54 with a comparator, have been mostly unsuccessful due to higher noise and limited load range compared to controllers using traditional analog converters. For example, a controller 102 using a comparator 104 is shown in FIG. 12. The architecture 106 is similar to the one of FIG. 7. In the circuit 106 of FIG. 12, the comparator 104 basically behaves as a 1-bit differential ADC which generates only the sign of the difference between the reference voltage 32 and the feedback signal 40. The comparator 104 has the advantage of a much simpler design and lower power consumption compared to a traditional ADC. It can also operate at lower power supply voltages. To further simplify the design, a simple integral compensator implemented with an up/down counter 108 can be used instead of a PID compensator. Loop gain can be controlled by changing the update rate of the up/down counter 108, via clock divider 110, or by scaling the output of the up/down counter. However, since the integral compensator implemented with the up/down counter 108 does not have zeroes, it cannot compensate properly for the large phase shift introduced by the LC filter when the load (Load) 36 is small. In fact, the phase shift increases as the load 36 is reduced. Stability can be achieved only by dramatically reducing the gain, but this is disadvantageously achieved at the expense of the response time. As the load 36 is reduced, the circuit 102 produces higher and higher ripple at the resonant frequency of the LC circuit, which disadvantageously limits the use of the converter 106 of FIG. 12 to a small range of loads. The performance of the converter 106 of FIG. 12 is also negatively affected by steady state limit cycles whose amplitude can be close to that of the ripple at the resonant frequency. This problem can be reduced by using a dead-zone comparator. With a dead-zone comparator, the up/down counter 108 is incremented or decremented only when the difference between the reference voltage 32 and the feedback signal 40 is outside the dead-zone of the comparator, otherwise the counter is not updated. However, the design of a dead-zone comparator is more complicated than the one of a traditional comparator. Also, the optimization of the dead-zone thresholds to reduce the limit cycle amplitude can be difficult. Digital differential input cells or low-voltage differential signal (LVDS) input cells, which are easily available in most of the digital libraries for integrated circuits, could be used as a comparator, but they do not contain a dead zone. With respect to the DPWM circuit 60, the same considerations made for FIG. 7 are valid for the controller 106 of FIG. 12 as well. DPWM circuits shown in FIGS. 9, 10 and 11 can be used.
Even though the controllers for switch-mode DC-DC converters (50,51) of FIGS. 7 and 8 require less analog circuitry than traditional analog controllers similar to the one of FIG. 5, they still need sophisticated analog circuits such as ADCs and DPWM circuits typically based on tapped-delay lines. In addition, the circuit 102 of FIG. 12 is simpler than the controller 50 of FIG. 7; however, a disadvantage is that the simplification has been obtained at the expense of performance. Furthermore, another disadvantage of the circuit 102 of FIG. 12 is that the circuit still requires a dead-zone comparator 104 instead of a classic comparator and a DPWM 60 based on tapped-delay lines or similar techniques.
Therefore, it would be highly desirable to have a digital controller for switch-mode DC-DC converters and method that is predominantly digital and configured for advantageously reducing problems encountered in the integration of traditional controllers. In other words, an improved digital controller and method for overcoming the problems in the art is desired.